1. Field of the Invention
The present invention relates to a technology of demultiplexing a multi-channel signal such as a stereo audio signal into multiple channel signals.
2. Description of the Related Art
In a case where a stereo audio signal having an L-channel signal (or Left channel signal) and an R-channel signal (or Right channel signal) is recorded as an audio signal to be recorded on an optical disk such as a CD (Compact Disk), the L-channel signal and the R-channel signal may often be mixed in recording. In order to perform audio processing on the R-channel signal and the L-channel signal separately, processing (which will be called “channel demultiplexing processing” hereinafter) is required for demultiplexing or separating the stereo audio signal read out from an optical disk into an L-channel signal and an R-channel signal and storing the signals into a memory such as a RAM (Random Access Memory). The conventional technology relating to this type of channel demultiplexing processing is disclosed in Patent Document 1 (Japanese Patent Application Laid Open Kokai No. 07-219080).
FIG. 1 is a block diagram showing a schematic configuration of a conventional data processing apparatus 10 which performs the channel demultiplexing processing. The data processing apparatus 10 includes a semiconductor circuit 100, which is an integrated circuit, a ROM (Read Only Memory) 104, and a RAM (Random Access Memory) 105. The semiconductor circuit 100 has a processor 101 such as a CPU, a first memory controller 102 connected to the ROM 104, a second memory controller 103 connected to the RAM 105 and an internal bus 201. The processor 101 is a bus master that is responsible for the right to use the internal bus 201, and the first memory controller 102 and the second memory controller 103 are bus slaves. The ROM 104 records a program to be executed by the processor 101. The processor 101 can load and execute an instruction program for channel demultiplexing from the ROM 104 through the first memory controller 102. The RAM 105 stores stereo data read out from an optical disk.
FIG. 2 is a schematic diagram for illustrating a routine of the channel demultiplexing processing. As shown in FIG. 2, the stereo data recorded in the RAM 105 cyclically includes 32 bit data {Ri,Li} (where i is one of 0 to 1023) containing a pair of R-channel data Ri of the higher order 16 bits and the L-channel data Li of the lower order 16 bits. The processor 101 in FIG. 1 first loads and executes an instruction program for channel demultiplexing from the ROM 104 through the first memory controller 102. Next, the processor 101 transmits a read instruction to the second memory controller 103 according to the instruction program to cause the second memory controller 103 to sequentially read out the 32 bit data {Ri,Li} from the RAM 105 and transfer the read 32 bit data {Ri,Li} to the processor 101 through the internal bus 201. The processor 101 demultiplexes the transferred 32 bit data {Ri,Li} into R-channel data Ri and L-channel data Li. The processor 101 further transfers the R-channel data Ri and the L-channel data Li to the second memory controller 103 through the internal bus 201 and transmits a write instruction to the second memory controller 103. The second memory controller 103 stores the R-channel data Ri and the L-channel data Li transferred from the processor 101 into selected areas in the RAM 105 according to the write instruction. As a result, as shown in FIG. 2, the R-channel data group only containing R-channel data R0 to R1023 and the L-channel data group only containing L-channel data L0 to L1023 are stored in the RAM 105.
However, the processor 101 may not perform most of the other processing than the channel demultiplexing processing while performing the channel demultiplexing processing since the channel demultiplexing processing imposes a large processing load on the processor 101 and requires a longer processing time. In particular, large latencies occur when the processor 101 reads out stereo data from the RAM 105 through the second memory controller 103 and when data is written into the RAM 105, which may disadvantageously reduce the performance of the entire system including the semiconductor circuit 100.